The present invention relates to a method of fabricating integrated circuits in microelectronic devices. In particular, the invention relates to a method of protecting a metal surface from oxidation for an indefinite time after a metal deposition step.
Integrated circuit manufacturers, especially those producing logic and custom logic devices, are moving to copper metallization for their most advanced products. Copper is replacing aluminum for metal interconnections in back end of the line processes because of its better conductivity and lower resistivity. However, copper diffuses more easily through dielectric materials that are used as insulating layers and requires a barrier material as a liner on the sidewalls of trenches before the metal is deposited by electroplating, chemical vapor deposition (CVD) or by sputtering methods.
A damascene process is used to build the back end of the device that includes metal wiring for interconnects. Typically, the process involves forming a stack comprised of one or more etch stop and barrier layers and one or more dielectric layers. A pattern is formed in the stack by first patterning a photoresist layer on the stack and then using the photoresist as an etch mask to transfer the pattern by etching into the damascene stack to form a feature such as a trench or via hole. In a dual damascene process, a liner is deposited in a trench and via hole and then a metal is simultaneously deposited to fill both the trench and via hole. The metal is deposited to a level above the damascene stack and is then lowered to a level that is coplanar with the top of the damascene stack by means of a chemical mechanical polish (CMP) step.
In the copper damascene process, the maintenance of a fresh copper surface after the deposition step has become a big challenge in the industry. Thin and discontinuous copper oxides exist intrinsically on substrates with an exposed copper surface in the presence of moisture and oxygen. Copper oxides lead to poor adhesion both at the copper/barrier layer and at copper/etch stop layer interfaces and enhance copper hillock formation during thermal processes. Thermal stress induces copper volume expansion and if there are any free spaces in the copper layer, hillocks will form. In addition, since an electroplated copper film has a polycrystalline structure with many grain boundaries, copper oxides will grow not only on the surface but also deep into a copper film along grain boundaries if the surface is exposed to moisture for a long period. The oxidized copper grain boundaries may extend into the trench below the top level of the damascene stack where they are very difficult to remove. Both single and dual damascene processes are employed in the industry.
Current manufacturing operations require a CMP step as soon as possible after the copper deposition to avoid copper oxide induced damage. This practice places unacceptable demands on a production line because of very short queue times (Q-times). Normal delays between processing steps may vary from minutes to hours or days and it is unrealistic to control one delay time to a very short interval at the expense of interrupting other operations which will cause a loss of throughput and increased cost of making a product.
Therefore, it is an advantage in the fabrication of devices employing copper damascene interconnects to be able to protect fresh copper surfaces such that they can be stored for indefinite periods of time without sustaining any copper oxide growth that will damage device performance. It will be a further advantage for an improved process not to require any new tools that will add to the manufacturing cost of the device and to be useful in protecting aluminum and aluminum/copper layers as well which are alternative metals for damascene structures that also form undesirable oxides.
Copper chelates or complexes with amines such as benzotriazole (BTA) have been employed in CMP slurries to form a protective coating on depressions in a metal surface while the higher points of the metal surface are being worn down by a combination of chemical etching and physical abrasion. U.S. Pat. No. 6,117,783 describes the use of BTA in combination with an oxidizing or reducing agent and an abrasive agent in an acidic media during a CMP process with copper. However, BTA is used only to control isotropic etching during the CMP process and does not remain on the substrate as a distinct layer and protective coating between process steps.
U.S. Pat. No. 5,770,095 describes an improved polishing method including BTA as part of a CMP slurry that also contains an etchant, oxidizer, and grinding media. The copper chelate with BTA only exists in the presence of etching, oxidizing, and grinding materials during the polishing process and never forms a distinct layer that can be stored for hours or days before the next step.
U.S. Pat. No. 6,207,559 describes the use of Cu+1(BTAxe2x88x921) or Cu+2(BTAxe2x88x921)2 as a protective layer in a stack that forms an electrical connection between the bond pad of a chip and the bond pad of a substrate in a memory device. The layer is less than 30 Angstroms thick and remains as a permanent layer in the device. The BTA is applied to the copper surface in a neutral solvent. If BTA was applied as part of an acidic or basic solution, cations or anions from the solution may become trapped in the Cu+(BTA) layer and result in a contamination that would degrade the device performance. Other amines that can form complexes with copper are also cited as useful for forming protective layers. When a layer becomes a permanent part of a device, strict controls on purity, thickness, thermal stability, and composition are required to maintain a maximum device performance. These controls can lead to a higher cost because of the effort and expense needed to guarantee the tight specifications.
Thus, a protective layer is needed for freshly deposited metal layers in damascene processes, especially those involving copper, which adds minimal cost to the manufacture of the device. Such a layer is best achieved when it is a sacrificial layer which exists for a period of only hours or days and does not become a permanent part of a device. The layer should be applied separately from other materials such as etchants and oxidants that could attack the sacrificial layer or underlying copper while the substrate is in storage. There is also a need for an improved process of applying a protective layer that is compatible with a high throughput mode involving little or no testing of the protective layer. It would also be desirable for the sacrificial protective layer to be applicable to the manufacture of other devices not involving damascene structures but requiring metal deposition techniques.
An objective of the present invention is to provide a sacrificial protective layer for a fresh metal surface after metal deposition and preferably before a chemical mechanical polishing (CMP) step in a damascene process. More specifically, the protective layer should prevent oxidation on the surface of the metal and along the grain boundaries below the metal surface. The protective layer must be stable and resistant to moisture and should have the capability to remain on the metal for an indefinite period of time before being removed in a subsequent process. The removal of the sacrificial layer should not add extra process time to fabrication process if it can be incorporated into an existing manufacturing step such as a CMP step.
Another objective of the present invention is to provide a method of forming a sacrificial protective layer on a metal layer on a substrate such that unreacted materials from the reagent used to treat the metal are removed prior to subsequent process steps. The process of forming the sacrificial layer and removing unreacted materials should be compatible with a low cost and high throughput mode of manufacturing.
Another objective is to provide a method of using the sacrificial protective layer during the fabrication of a microelectronic, micro-electromechanical, or LCD device in which a metal is deposited on a substrate and an indefinite storage time occurs before the next process step. The sacrificial protective layer prevents the underlying metal from forming oxides during the storage period that would cause a degradation in device performance.
These objectives are achieved in the following embodiments of the present invention. In one embodiment, the present invention is a sacrificial protective layer that is formed on a fresh metal surface and prevents metal oxides from forming. In a preferred example, the layer is a monolayer formed by applying an amine to a copper layer on a substrate which reacts to form a copper complex with the amine. The copper complex is hydrophobic and prevents moisture from reacting with the underlying copper to produce oxides. The layer is stable and can remain on the substrate for an indefinite storage time. It forms a conformal coating on the copper surface such that an equal thickness is formed which is independent of the slope of the surface. Thus, the copper surface of the substrate is protected to an equal extent no matter if the localized surface is perpendicular to the substrate, parallel to the substrate, in a depression or on a higher point than surrounding areas. This feature is distinguishable from a protective coating formed during a CMP process where the higher points of the surface are less protected and preferentially removed than lower points on the surface.
The method of application can involve dipping, spraying, spin coating, or chemical vapor deposition (CVD) in order to improve throughput and reduce cost. The most efficient method of amine application and removal of amine can depend on the tools which are more available in the manufacturing line. If the amine is applied in a solution, the substrate is rinsed with DI water and dried after the application to prepare it for storage and a subsequent CMP step. If the amine is applied by spraying or in a CVD process, the amine is removed in a vacuum, by baking, or by a combination of the aforementioned conditions.
In another embodiment, the sacrificial protective layer is formed on a metal surface during a damascene process and is removed in a subsequent CMP step.
In another embodiment, the sacrificial protective layer is formed on a metal layer that has been deposited on a substrate during the fabrication of a microelectronic, micro-electromechanical, or LCD device. The substrate is stored for an indefinite period of time. The sacrificial layer is then removed by a process that does not degrade the performance of the underlying layer prior to the next step in the fabrication process.